/* * gt64011.h: Galileo PCI system controller * Copyright (c) 1998 Algorithmics Ltd */ #ifdef __ASSEMBLER__ /* offsets from base register */ #define GT64011(x) (x) /* device is littleendian, so data may need to be swapped */ #ifdef GALILEO_PORT #define htoll(x) ((((x) & 0x00ff) << 24) | \ (((x) & 0xff00) << 8) | \ (((x) >> 8) & 0xff00) | \ (((x) >> 24) & 0x00ff)) /*#define ltohl(x) htoll(x)*/ #else #define htoll(x) (x) /* #define ltohl(x) (x) */ #endif #else /* !__ASSEMBLER */ /* offsets from base pointer, this construct allows optimisation */ static char *const _gt64011p = (char *) PA_TO_KVA1(GT64011_BASE); #define GT64011(x) *(volatile unsigned long *)(_gt64011p + (x)) /* device is littleendian, so data may need to be swapped */ #ifdef GALILEO_PORT #define htoll(x) ({ \ unsigned int v = (unsigned int)(x); \ v = (((v & 0x00ff) << 24) | \ ((v & 0xff00) << 8) | \ ((v >> 8) & 0xff00) | \ ((v >> 24) & 0x00ff)); \ v; \ }) #define ltohl(x) htoll(x) #else asjdsajd #define htoll(x) (x) #define ltohl(x) (x) #endif #endif /* __ASSEMBLER__ */ /* CPU configuration */ #define GT_CPU_CFG GT64011(0x000) #define GT_CPU_CFG_WriteMode (1<<11) #define GT_CPU_CFG_Endianess (1<<12) /* Processor Address Space */ #define GT_PAS_RAS10LO GT64011(0x008) #define GT_PAS_RAS10HI GT64011(0x010) #define GT_PAS_RAS32LO GT64011(0x018) #define GT_PAS_RAS32HI GT64011(0x020) #define GT_PAS_CS20LO GT64011(0x028) #define GT_PAS_CS20HI GT64011(0x030) #define GT_PAS_CS3BOOTLO GT64011(0x038) #define GT_PAS_CS3BOOTHI GT64011(0x040) #define GT_PAS_PCIIOLO GT64011(0x048) #define GT_PAS_PCIIOHI GT64011(0x050) #define GT_PAS_PCIMEMLO GT64011(0x058) #define GT_PAS_PCIMEMHI GT64011(0x060) #define GT_PAS_INTDEC GT64011(0x068) #define GT_PAS_BUSERRLO GT64011(0x070) #define GT_PAS_PCIMEM1LO GT64011(0x080) #define GT_PAS_PCIMEM1HI GT64011(0x088) #define GT_PAS_LOMASK_Low 0x7ff #define GT_PAS_LOSHIFT_Low 0 #define GT_PAS_HIMASK_High 0x07f #define GT_PAS_HISHIFT_High 0 /* DRAM and Device Address Space */ #define GT_DDAS_RAS0LO GT64011(0x400) #define GT_DDAS_RAS0HI GT64011(0x404) #define GT_DDAS_RAS1LO GT64011(0x408) #define GT_DDAS_RAS1HI GT64011(0x40c) #define GT_DDAS_RAS2LO GT64011(0x410) #define GT_DDAS_RAS2HI GT64011(0x414) #define GT_DDAS_RAS3LO GT64011(0x418) #define GT_DDAS_RAS3HI GT64011(0x41c) #define GT_DDAS_CS0LO GT64011(0x420) #define GT_DDAS_CS0HI GT64011(0x424) #define GT_DDAS_CS1LO GT64011(0x428) #define GT_DDAS_CS1HI GT64011(0x42c) #define GT_DDAS_CS2LO GT64011(0x430) #define GT_DDAS_CS2HI GT64011(0x434) #define GT_DDAS_CS3LO GT64011(0x438) #define GT_DDAS_CS3HI GT64011(0x43c) #define GT_DDAS_BOOTCSLO GT64011(0x440) #define GT_DDAS_BOOTCSHI GT64011(0x444) #define GT_DDAS_ERROR GT64011(0x470) #define GT_DDAS_LOMASK_Low 0xff #define GT_DDAS_LOSHIFT_Low 0 #define GT_DDAS_HIMASK_High 0xff #define GT_DDAS_HISHIFT_High 0 /* DRAM Configuration */ #define GT_DRAM_CFG GT64011(0x448) #define GT_DRAM_CFG_RefIntCntMASK 0x00003fff #define GT_DRAM_CFG_RefIntCntSHIFT 0 #define GT_DRAM_CFG_RefIntCnt(x) (((x)<